In serial data communication system, jitter plays a key role in data transfer and system timing. Noise from power supply will degenerate the jitter performance of data communication system, so low noise and high PSR V-I Convert for VCO, which generates clock for system, is required.
Conventional V-I Converter uses unit gain buffer, which is shown as FIG. 1, while this structure has several disadvantages. First, unit gain buffer brings addition poles to PLL Loop, which complicates the design of PLL Loop. Second, it's hard to realize high Power Supply Rejection (PSR), and also device noise from unit gain buffer often degenerate the phase noise of VCO, making the jitter performance of PLL worse.